With the continuous development of semiconductor technology, the technical node of the semiconductor process has become smaller and smaller by following the Moore's law. In order to adapt to the shrinking of the technical node, the channel length of MOSFETs has to be continuously shrunk. The shrinkage of the channel length brings up the advantages of increasing the device density; and increasing the switch speed of the MOSFET, etc.
However, with the continuous shrinking of the channel length of the semiconductor device, the distance between the source region of the device and the drain region of the device is also correspondingly reduced. The decreased distance between the source region and the drain region may cause the control ability of the gate structure to the channel to be weakened; and the pinch-off of the gate structure to the channel may become more and more difficult. Thus, the sub-threshold leakage phenomenon, i.e., the short-channel effects (SCEs), may easily happen.
Therefore, in order to adapt to the requirements for shrinking the semiconductor devices with a certain ratio, the semiconductor process has gradually switched from planar MOSFETs to three-dimensional transistors which have better performance. For example, fin-field effect transistors (FinFETs) have been developed as the three-dimensional transistors. In a FinFET, the gate structure may at least control the ultra-thin body (Fin) from two sides, thus the control ability of the gate structure to the channel may be significantly greater than the control ability of the gate structure in a planar MOSFET; and the SCEs may be better suppressed. Comparing with other devices, FinFETs may have a better compatibility with the existing fabrication methods of integrated circuits.
However, the electrical properties of the FinFETs formed by existing methods may need further improvements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.